New strategy enhances 2D transistor dielectric layers

Transistors based on two-dimensional (2D) semiconductors, such as molybdenum disulfide (MoS₂) and tungsten diselenide (WSe₂), could outperform conventional silicon-based transistors, while also being easier to reduce in size. To perform well, these transistors need to be based on high-quality dielectric materials, which can be difficult to prepare.

Researchers at Nanyang Technological University, Nanjing University of Aeronautics and Astronautics recently introduced a new promising strategy to prepare the dielectric materials for these transistors. Their approach, outlined in a paper published in Nature Electronics, was successfully used to deposit an ultrathin and uniform native oxide of gallium Ga₂O₃ on the surface of MoS₂.

“Traditional methods of preparing dielectric layer, such as atomic layer deposition (ALD), encounter quality problems because of the high-quality surface of 2D semiconductors without sufficient nucleation points, especially at thin thicknesses down to a few nanometers,” Kongyang Yi, first author of the paper, told Tech Xplore.

“Back in 2017, a pioneering paper reported a method of preparing ultrathin and uniform oxide from liquid metal. After reading it, I started wondering whether these oxides could possibly be used as dielectric layer in transistors based on 2D semiconductors without the problems mentioned above.”

Building on this previous research paper, Yi and his colleagues set out to test the potential of this approach using the oxide Ga₂O₃, which is known to exhibit robust dielectric properties. Their objective was to devise a reliable method to integrate this oxide in 2D transistors, specifically as dielectric layer, and then assess the performance of the resulting transistors.

“The surface-tension-driven method used to prepare large-scale Ga₂O₃ was the unique method proposed in this work,” explained Yi. “The process includes a few steps. First, pressing a drop of liquid gallium over the target substrate and freezing it to solid state, leaving a thin solid gallium film. Second, heating it rapidly.”

When the researchers heated their sample, the thin solid gallium film instantly melted. As this liquid metal has a very strong surface tension, the molten liquid gallium aggregated automatically, depositing its native oxide skin onto the substrate.

“The unique advantage of our approach is that it can be used to easily prepare an ultrathin and uniform oxide with high quality on the surface of 2D semiconductors, without potential problems by traditional deposition methods,” said Yi. “Using this method, we prepared ultrathin and uniform Ga₂O₃ directly on 2D semiconductors (MoS₂), and then fabricated the transistors.”

The team of researchers ran a series of tests to assess the potential of their metal oxide as dielectric layer. Notably, ultrathin and uniform Ga₂O₃ less than 3 nm was easily integrated in MoS₂ transistors via van der Waals interaction. 2D transistors fabricated using their strategy exhibited a subthreshold swing down to 60 mV dec⁻¹, an on/off ratio of 10⁸ and a gate leakage down to around 4 × 10⁻⁷ A cm⁻².

A key advantage of their approach is that a high-quality van der Waals interface can be easily obtained, benefiting the device performance. Meanwhile, it is easy to implement and thus could contribute to the large-scale fabrication of 2D transistors

“Other potential methods of better using this native oxide of gallium (controlling the thickness and large-scale preparation) were reported in recent years,” said Yi. “We believe with more improvements in the future, this oxide could be used to fabricate various electronic devices.”

The recent study by this team of researchers opens new possibilities for the fabrication of 2D transistors with dielectric layers based on gallium oxide. In the future, the integration strategy introduced by Yi and his colleagues could also be used to fabricate more complex circuits with a broader range of functions.

“We are now planning to improve the surface-tension-driven method,” added Yi. “Currently, it was realized by manual operations and wafer-scale preparation was not perfect compared with traditional methods. We hope we can realize high-quality preparation over a whole wafer and demonstrate more wafer-scale applications such as integrated circuits.”

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