New framework designs scalable 3D transistors based on 2D semiconductors

Conventional electronics based on silicon are approaching their limits in terms of performance and scalability. In recent years, engineers have thus been trying to introduce alternative designs that could help reduce the size of electronic components while also improving their speed and energy efficiency.

Researchers at the University of California- Santa Barbara have devised a new framework that could contribute to this quest, enabling the fabrication of scalable three-dimensional (3D) field-effect transistors (FETs) based on two-dimensional (2D) layered semiconductors. Their proposed approach, outlined in Nature Electronics, accounts for key factors that can influence the performance of these transistors, including so-called Schottky contact effects and inclusive capacitance.

“Our research group was among the early contributors to emphasize the importance of a multi-gate architecture for achieving realistic sub-10 nm FETs, even with atomically-thin channels based on 2D semiconductors,” said Kaustav Banerjee, senior author of the paper, in an interview with Tech Xplore.

“This perspective was further explored in our recent work on future transistors, where we collaborated with leading experts from the semiconductor industry to highlight the potential of three-dimensional transistors.”

The main objective of the recent work by Banerjee and his colleagues was to demonstrate the potential of atomically thin 2D layered materials for the fabrication of next-generation 3D-FETs with various architectures. In addition, the researchers hoped to gain insight into what material, architecture and design is optimal for these transistors.

While conducting their study, they discovered that 2D materials can also be uniquely engineered to create an entirely new transistor architecture, which they dubbed nano-plate FET (NPFET). This architecture could exhibit improved performance and a greater integration density.

“Our proposed framework for designing scaled 3D transistors involves employing quantum transport formalism for simulating carrier transport, using a commercially available technology computer-aided design (TCAD) tool called QTX,” explained Banerjee. “This tool leverages the non-equilibrium Green’s function framework (NEGF), one of the most powerful quantum transport approaches.”

For different variants of the NEGF function, the researchers employed an effective mass-based approach. This method was found to be computationally efficient and accurate while also accounting for energy-band non-parabolicity effects, satellite valleys and the finite energy width of these valleys.

“These input parameters were calculated with density functional theory (DFT) simulations, an ab-initio method, and then imported into QTX,” said Banerjee. “We also considered the effect of non-ideal contact resistance and carrier mobility to conduct more thorough simulations.”

The results of simulations performed by the researchers suggest that 2D semiconductor- based 3D-FETs can achieve superior performance compared to silicon-based FETs. The channel length of these 2D material-based 3D-FETs was scaled down to around or below 7nm and the material that yielded the greatest gains was WS₂.

“The increased drive current, coupled with the reduced device capacitance due to the thinness of the 2D semiconductor compared to silicon, enhances the overall energy-delay-product (EDP) of circuits designed with 2D semiconductor-based transistors,” said Banerjee. “Additionally, we have provided a comprehensive blueprint for designing 2D semiconductor-based 3D-FETs to support future CMOS scaling.”

To scale transistors, the new NPFET architecture introduced by this research team leverages the thinness and vertical stacking of 2D semiconductors. Compared to comparable 3D-FET architectures introduced in previous studies, this architecture could offer important benefits in terms of both integration density and performance.

“Our future research endeavors will focus on collaborating closely with industry partners to expedite the integration of these materials and designs into mainstream CMOS processes,” added Banerjee. “Additionally, we aim to enhance our simulations by incorporating a broader range of non-ideal effects, such as defect scattering and self-heating. This will provide deeper insights and support to experimental researchers in the field.”

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